1. Field of the Invention
The present invention generally relates to the art of microelectronic integrated circuits, and more specifically to an integrated circuit interconnect structure with back reflection suppressing electronic "speed bumps".
2. Description of the Related Art
High speed digital circuits, defined as those having digital pulses exceeding 1 Mhz, exhibit behavior significantly different than that seen in lower speed circuits. This behavior is illustrated in FIGS. 1A-1C to which reference is now made.
FIG. 1A illustrates an interconnect 10 connecting a driver 14 and an electrical contact 12, and FIGS. 1B and 1C are voltage vs. time graphs respectively illustrating a voltage pulse 16 produced by driver 14 and a resultant signal 17 at the interface between interconnect 10 and contact 12.
For example, pulse 16 may develop significant back reflection at the interface between the interconnect 10, made of metal or polysilicon, and the electrical contact 12, made of silicon. The back reflection propagates backwards along the interconnect 10, bouncing off the driver 14 and causing a ringing effect.
Furthermore, the back reflection propagates along any other interconnects (not shown) to which interconnect 10 may be connected. Thus, the back reflection causes spurious, uncontrollable noise throughout the integrated circuit in which interconnect 10 is located.
The back reflection also increases the effective "rise time" of the pulse arriving at contact 12. The original pulse 16 transitions from a first value of 0, such as might indicate an OFF state, to a second value of 1, such as might indicate an ON state, during a "rise time" of T.sub.1, where T.sub.1 is typically 500 pico sec. The pulse 17 (FIG. 1C) with the back reflection, on the other hand, has a much larger effective rise time, denoted T.sub.2, on the order of 2 nanoseconds.
Thus, the back reflection reduces the maximum operating speed of the integrated circuit (since T.sub.2 is larger than T.sub.1), and adds significant, uncontrollable noise to the operation. In high speed circuits, such a situation is untenable, especially in circumstances of high ON/OFF switching speeds.
In a second example, illustrated in FIGS. 2A and 2B to which reference is now made, a driver 15 is connected to a receiver transistor 18 (FIG. 2A) via an interconnect 21. A second interconnect 22, located nearby, is connected to a second receiver transistor 24.
In certain situations, the two interconnects 21 and 22 are capacitively cross-coupled such that if a pulse 26 having a very sharp transition from 1 V to 0 V propagates along interconnect 21, it induces a similar pulse 28 in interconnect 22.
Receiver transistor 18 will transition in a normal manner from 1 V to 0 V. However, if receiver transistor 24 is already at 0 V, the pulse along interconnect 22 will induce transistor 24 to transition to a negative voltage value, typically of -0.7 V, which is the latched state. Once receiver transistor 24 is "latched up", it will not respond to any incoming signals
The above described phenomenon is known as the "culprit-victim" problem, where interconnect 21 is the culprit and interconnect 22 is the victim, and is primarily caused by very sharp transitions. The sharp transitions also cause abrupt changes in the voltage level of the power supply because of the significant current demand of the transition.